A Shifting Chip Strategy
GF Securities reported that Google selected MediaTek over both Broadcom and Qualcomm for the TPUv9 program, and believes MediaTek is also the frontrunner for the TPUv10. The brokerage raised its projections for MediaTek’s ASIC-related revenue as a result. seekingalpha.com tipranks.com
The Triggerfish chip will combine both training and inference capabilities into a single processor, a departure from Google’s eighth-generation approach, which split the workload between two separate chips: the Broadcom-designed “Sunfish” for training and the MediaTek-designed “Zebrafish” for inference. Mass production of Triggerfish is expected in Q4 2027, with volume ramp in 2028. thenextweb.com wccftech.com
Broadcom Under Pressure
The news adds to existing pressure on Broadcom. In early June, the company’s shares fell roughly 12-14% after its fiscal second-quarter earnings report disappointed investors, with AI chip revenue guidance of $16 billion for the third quarter coming in below analyst expectations of $17.2 billion. A subsequent Wedbush note flagging the potential TPUv9 shift to MediaTek sent shares lower again later in the month. reuters.com finance.yahoo.com tradingview.com
However, the picture is more complex than a simple replacement. In April 2026, Broadcom filed an 8-K with the SEC confirming a long-term agreement with Google to develop and supply custom TPUs through 2031. JPMorgan noted in mid-June that Broadcom remains responsible for its own TPUv9 variant and that the five-year agreement covers four TPU generations. Broadcom’s TPUv9 project, reportedly codenamed “Whalefish,” targets mass production in 2028 but faces what analysts describe as disadvantages in process node and HBM capabilities relative to the MediaTek-led designs. tradingview.com stocktitan.net news.futunn.com
MediaTek’s Rising AI Ambitions
MediaTek’s deepening relationship with Google began with the TPU v8i inference chip and has now expanded to encompass the unified TPUv9 architecture. The Triggerfish design features an expanded SRAM cache — estimated at two to three times larger than its predecessor — and a new CPU tile housed within the same package as the primary compute die, engineered to manage switching between AI training and inference workloads. Both TPUv9 variants are expected to be fabricated on TSMC’s advanced process nodes. wccftech.com
Google’s multi-supplier approach mirrors broader industry trends among hyperscalers seeking to diversify their custom silicon supply chains while driving down costs — a motivation analysts have flagged since early reports of the Google-MediaTek collaboration first surfaced in March 2025. moomoo.com siliconangle.com
